High performance field effect transistors have been made in semiconductor substrates which utilize a very small amount of surface area. However, advantages provided by miniaturization are sometimes negated by mask tolerances required to insure proper alignment between successive masking steps in a process. Furthermore, the need for metallic or conductive contacts and for crossover arrangements for wiring associated with the transistor increases considerably the required surface area and the complexity of the process for making the transistor. Consequently, it is desirable to use processes with self-alignment features, a minimum number of masking steps and a provision for a crossover arrangement which does not require forming an insulating layer above the oxide surface of the semiconductor substrate between metallic or conductive layers.
In IEEE Transactions on Electron Devices, December 1973, in an article entitled, "Three-Mask Self-Aligned MOS Technology", by C. C. Mai et al, pages 1162 to 1164, there is described a simple three mask process for making a field effect transistor.
However, this transistor, having an aluminum gate, uses a process which does not provide self-aligned contacts and it leaves an exposed area near the gate region introducing a potential contamination problem. In commonly assigned U.S. Pat. No. 3,958,323 by F. H. De La Moneda, filed Apr. 29, 1975, there is disclosed another simple three mask process for making a transistor but this process does not provide for self-aligned contacts nor is there a crossover provision which can be utilized by, e. g., a simple formation of an extension of the gate electrode since diffusions in the substrate must be provided after the gate electrode is formed. In U.S. Pat. No. 3,699,646, by L. L. Vadasz, filed Dec. 28, 1970, there is provided a process for making field effect transistors which discloses a provision for making contacts between the gate electrode of a first device and a current carrying electrode of a second device but no provision is made for a crossover arrangement without introducing additional steps to complicate the process. The process disclosed in the above-identified Vadasz patent does have certain advantages over other processes in the prior art in that the process uses polysilicon gates and interconnecting lines which are capable of being oxidized and thus they are self-insulating. For a more detailed description of the advantages of polysilicon gate technology reference may be had to Solid-State Electronics, Pergamon Press, 1970, Vol. 13, pp. 1125-1144. Also, it has been found that transistors may be advantageously made by employing metal silicides, as for example, described in U.S. Pat. No. 3,777,364, by R. D. Schinella et al, filed July 31, 1972.